Electronics - Verilog - Instantiating a module from another module

You understood the structural description in Verilog.

You are currently using the Altera DE1 board.

Fine.

But you want more because you really want to understand how it works through a real example with your board.

And not a difficult one of course, a beginner tutorial with an easy example of instantiating a module from another module.

Let's get started.

Explanation

We are going to create two files: an abstract and an object.

Object is an instantiation of abstract.

Really easy if you understand the object paradigm.

If you don't know what is this, just see the abstract as something that is needed to be instantiate to be real.

So our object will be sent to the board. The abstract cannot.

Once you have copied these two files, set object.v as top-level entity.

Then start compilation and send it to the board.

Each time you click KEY0 or KEY1, LEDR3 is lit.

Code

abstract.v

// module abstract

module abstract(

    input wire i0, i1,
    output reg result

);

reg r0, r1;

always @(i0, i1)
begin
    r0 = ~i0 & ~i1;
    r1 = i0 & i1;
    result = r0 | r1;
end
endmodule

object.v

// module object

module object(

    input wire [3:0] KEY,
    output wire [8:0] LEDR

);

abstract(
    .i0(~KEY[0]),
    .i1(KEY[1]),
    .result(LEDR[3])
);

endmodule

Conclusion

A really easy example of how using modules in order to instante them.

If you get this example, the world is yours.

Well done, you've made it.