Every language needs to handle numbers.
With Verilog we're going to see that numbers need to have an explicit base system to avoid errors.
Each base system has a radix.
This radix is the number of unique digits making up a base system.
For example the radix of the hexadecimal system is 16.
So all digits of the hexadecimal base are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F.
It's the same for other ones such as:
More systems exist but they're not used with Verilog (and HDL in general), so we won't talk about them in this tutorial.
For our example, we're going to use the DE1 board from Altera in order to switch on a LED.
So first of all, we have to specify that we want to use SystemVerilog instead of just Verilog.
Two ways to do that:
1) If you chose to create directly a SystemVerilog file, you would have nothing more to do.
The file's extension would be ".sv".
2) If you chose to transform a Verilog file into a SystemVerilog, you would have to set it into Quartus.
After creating a Verilog file, you have to click > Assignments > Settings > Analysis & Synthesis Settings > Verilog HDL Input > SystemVerilog.
OK, let's continue.
The LED is the first one on the right, called LEDG0.
In the code below there is something very weird if you don't look at it closely.
And this kind of practice is source of error.
Indeed, data1 is assigned with the value: 36_6_451_4_723.
The data2 is assign with the value: 1'b1.
In the always @ block we test if data1 is equal to data2.
Spontaneously one says: no.
If you run this code, you should see that the green LED is now lightning.
And that was wrong, data1 and data2 were equal.
Because in the first value, data1, we set its value with 36_6_451_4_723.
Notice that in Verilog, one can use underscore (_) in numbers, often to have a better readability with long numbers.
So this number is the same as 3664514723 or 3_664_514_723.
But this doesn't explain why it's equal to data2.
In data2 we set a value of 1'b1.
And in this value we could split up it like that:
OK, now if we see at this number we could say that data2 is equal to a binary with a value of 1.
And what the compiler will say during its compilation is:
Warning (10230): Verilog HDL assignment warning at number.v(12): truncated value with size 32 to match size of target (1)
Indeed, in the if statement we're comparing only the last bit of each of them.
In our example, data1 = 3664514723.
This number in binary is equal to: 11011010011011000000111010100011.
So if we compare the last digit of each, we will see that these digits are equal.
As a result we'll have:
data1 = 11011010011011000000111010100011
data2 = 1
And finally in the if statement we've:
11011010011011000000111010100011 = 1
If you changed data1 by 3664514722 it would have been false and the LEDG wouldn't have been lighted.
More generally we can say that if a decimal number is an odd number it'll be equal to 1'b1 and if it's an even one, it won't.
// Verilog and numbers module number ( input CLOCK_50, output [0:0]LEDG ); reg data1; reg data2; reg data3; assign data1 = 36_6_451_4_723; assign data2 = 1'b1; assign data3 = 1; always @ (posedge CLOCK_50) begin if (data1 == data2) begin LEDG <= data3; end end endmodule
It's a good practice to always use explicit base system when using numbers into Verilog code.
Anyway I'm sure you've understood this tutorial.
So well done you've made it.