After installing Quartus II command-line interface for Windows you're ready to play with it.
The board used in this tutorial is the DE1 (EP2C20F484C7) with a Cycl0ne II FPGA.
The langage will be Verilog.
First of all
We're going to create a project from Quartus GUI, write a file in Verilog and just after use the command-line interface (CLI) to make all stuff necessary to have a functional project.
From Quartus > File New Project Wizard:
> Next > Next:
Select EP2C20F484C7 in the Available devices list > Next > Simulation > ModelSim-Altera > Format(s) > Verilog HDL > Next > Finish.
Then File > New > Design Files > Verilog HDL File > OK.
Write down the following code within this new Verilog file and save it as badprog1.v.
// badprog1.v module badprog1(a, b, c); input a; input b; output c; endmodule
With this simple easy basic code, it'll be possible to compile the project.
For that, open Cygwin and go until the directory where there's your project, for example mine is:
Once there, type this:
quartus_sh --flow compile badprog1
The --flow option allows to specifiy the command you would like to use, such as compile and the entity, in our case badprog1.
To know how to use the flow option, type it:
You could do the same with all options.
A simple quartus_sh --help we'll help you to know every option available.
So, the compile command will create the four following directories with files inside:
To see that, you can remove all directories and relaunch the command.
To remove db, you'll certainly have to close Quartus GUI first.
This time, instead of typing each command at a time, we're going to create a file with all those commands inside.
So let's create a file named code.sh (sh = shell) and, inside, add the following code:
#!/bin/sh PROJECT="badprog1" TOP_LEVEL_ENTITY="badprog1.v" DEVICE_FAMILY="Cyclone II" DEVICE_PART="EP2C20F484C7" PACKING_OPTION="minimize_area" quartus_map $PROJECT --source="$TOP_LEVEL_ENTITY" --family="$DEVICE_FAMILY" quartus_fit $PROJECT --part="$DEVICE_PART" --pack_register="$PACKING_OPTION" quartus_asm $PROJECT quartus_sta $PROJECT
To launch this code from Cygwin, type:
Every command line is executed one after another.
In the file you can see variables written in uppercase.
The variable names are free, you could write yours, but don’t forget to change them also, when you call them, that is to say in the command line itself.
For example TOP_LEVEL_ENTITY must be correct when you use it with:
quartus_map $PROJECT --source="$TOP_LEVEL_ENTITY" --family="$DEVICE_FAMILY"
Furthermore don’t forget to add double quotes, even in the code line, otherwise it won’t work.
You’re maybe wondering where data is saved once created with a CLI or directly from the Quartus GUI.
You could find it in the badprog1.qsf.
Actually a file with a .qsf extension means: Quartus Settings File.
For example in my badprog1.qsf there is:
set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C20F484C7 set_global_assignment -name TOP_LEVEL_ENTITY badprog1 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:52:51 MARCH 03, 2014" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name SOURCE_FILE badprog1.v set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII MINIMIZE_AREA
And you can see that information specified before has been saved in the badprog1.qsf file.
It’s possible to easily use this file for a new project, just copy/paste it.
This file is by default modified each time you change settings.
So if don't want a such behaviour, it can be stopped with the following command line, for example for the reading assignments:
quartus_fit badprog1 --read_settings_files=off
Do the same with write for the writing assignments.
Quartus_sh > (.v, .vhd, .vqm, .tdf, .bdf, .edf) >
quartus_sta > quartus_eda > (.vo, .vhd, .sdo)
As you certainly see, in your project directory there’s a directory called output_files.
Within there’re some files with one or more extensions.
If they have two extensions, like badprog1.fit.rpt, it means that you've used the quartus_fit executable to generate it.
So a report (.rpt) will be generated and you will be able to open and analyze it.
In this part, we’are going to create a new project without the Quartus II GUI, that’s only with command-line interface.
Create a new directory to create a new project:
Then go inside:
If you type:
You should be there:
To create a new project you could use the GUI, easy, but there is another way to do so with the CLI.
quartus_sh --tcl_eval project_new badprog2
Two new files have been added:
The db directory is also created.
There’s also a mix between the GUI and Cygwin: QFlow.
QFlow is a Tcl console window with GUI.
To open it, type from Cygwin:
The QFlow window’s opened with a tcl> prompt.
A new project has been created.
If you checked the current directory, you could see two new files:
You can remove those two new files.
To handle easily Tcl command scripts, it’s possible to create a file only for a Tcl use.
By default, when you do not specify anything, the family device will be Cyclone IV GX.
To check it, open the badprog2.qsf file and you will find it.
Let's change it.
So, create a new file code.tcl, open it and write it down:
project_new badprog3 -overwrite set_global_assignment -name FAMILY "Cyclone II"
Then from Cygwin:
quartus_sh -t code.tcl
The badprog3.qpf and bapdrog3.qsf are now recreated.
But this time, if you checked the badprog3.qsf file you could see that the family is Cyclone II as we’ve specified it.
So if you did the same for all assignments, it would be added in the Quartus Settings File (.qsf).
To have a better specification let’s add the following assignments:
project_new badprog3 -overwrite set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE "EP2C20F484C7" set_global_assignment -name BDF_FILE "badprog3.bdf" set_location_assignment -to clock PIN_L1 project_close
We have just assigned the PIN_L1 to the clock signal but it's possible to assign all signals with pins from the DE1 board.
OK, now we’ve to create the badprog3.v Verilog file in order to compile the project:
// badprog3.v module badprog3 (enable, clock, counter); // declaration input enable; input clock; output reg [7:0] counter; // always always @(posedge clock) begin if (enable) begin counter = counter + 1'b1; end else begin counter = 0; end end endmodule
Finally retype the following command line:
quartus_sh --flow compile badprog3
The project has fully compiled with assignments specified.